Fabrication of semiconductor devices involves the application of numerous fabrication steps. Each of the fabrication steps extracts a cost in terms of time and handling. Generally, a process that involves fewer handling steps generally produces electronic devices at a much lower cost than a process that produces the same quality devices using more handling steps.
Each structure in a semiconductor device is produced by a series of fabrication steps. One such structure is a premetal interlayer dielectric deposition. A premetal interlayer dielectric is a dielectric layer that is typically formed between polysilicon and a metal interconnect layer so that all of the devices underlying the metal interconnect layer are electrically isolated.
A conventional process for forming a premetal interlayer dielectric on a semiconductor wafer requires many fabrication steps. These steps include a low temperature oxidation deposition step to form a barrier layer and cleaning operation prior to low temperature oxidation. The cleaning operation is performed in a different tool (a sink) than the low temperature oxidation tool (a furnace). Following the low temperature oxidation, the wafer is again removed from the furnace for cleaning. After cleaning, a boron-phosphorous TEOS deposition is performed in a PECVD reactor to form a second layer of oxide film. Densification of the two-layer film is achieved by thermal cycling in a furnace. Densification reflows the oxide at elevated temperatures and results in some planarization of the surface of the semiconductor wafer. Following densification, the wafer is again cleaned. The wafer is then inspected for BPO.sub.4 crystal defects that may occur in densification. The wafer is then etched back in a reactor to give the final form of the premetal interlayer dielectric. The many steps used in this process result in an increase in fabrication costs.
What is needed is a method for depositing a premetal interlayer dielectric that greatly reduces handling steps and thus reduces fabrication costs.